Expanded memory addressing scheme

ABSTRACT

A 31-bit addressing scheme is compatible with current 24-bit addressing schemes and allows an address space of 2 GB to be created. The shared area of the operating system is divided into two separate areas (230, 260), one (230) located at the bottom of the address space and the other (260) at the top of the address space. Between the shared areas (230, 260), a continuous private area (240, 270) is available for use by the applications software. In one embodiment of the invention, the size of the bottom shared area (230) is limited to 1 MB blocks so optimizing the use of private area (230) by applications programs written for 24-bit addressing.

TECHNICAL BACKGROUND OF THE INVENTION

The invention concerns an N-bit addressed memory containing private areaand shared area, and a method for addressing this memory.

DESCRIPTION OF THE PRIOR ART

The memory management techniques of a computer operating system servetwo functions. Firstly, they optimize the use of the available storagemedia to be totally transparent to the applications programmer. Theconcepts behind such techniques are described in a number of differentpublications. Among these are "Operating Systems: Structure andMechanisms" by Philippe A. Janon, Academic Press, Inc., London, 1985, pp103-143, "Operating Systems: Design and Implementation" by Andrew S.Tanenbaum, Prentice Hall, Englewood Cliffs, 1987, pp 191 ff, and"Operating System Concepts" by James L. Peterson and AbrahamSilberschatz, Addison-Wesley, Reading, Mass., 1983, pp 131-188.

In the IBM VSE/Enterprise Systems Architecture Version 1 Release 1operating system a 24-bit memory addressing scheme is used which allowsaddresses spaces only up to a maximum size of 16 MB. The conceptualinformation relating to storage management in this operating system isdescribed in "IBM VSE/Enterprise Systems Architecture: Guide to SystemFunction, Version 1 Release 1", IBM Corp., 1990, Publication NumberSC33-6511-00 which is hereby incorporated by reference.

As application programs for computers have become larger, the 16 MBrestriction imposed by the use of 24-bit addressing has become alimiting factor in its development. Thus a need has arisen to increasethe amount of memory space available by moving to an addressing schemeemploying a larger number of bits. However, in order to protect customerinvestment, the new addressing scheme should allow software written fora 24-bit addressing scheme to continue to run under the expandedoperating system.

The IBM MVS/XA operating system was also originally designed for a24-bit addressing scheme and thus was also limited to address spaces of16 MB maximum. However, to enable it to run on computers witharchitectures which allow 31 bits to be used, such as the IBM S/390machines, it has been adapted to a 31-bit addressing scheme which allowsup to 2 GB of storage to be directly addressed. FIG. 1 shows the memorystructure used by MVS/XA in order to ensure that compatibility withapplication programs written for 24-bit addressing scheme is preserved.The memory structure 10 comprises a number of virtual address spaces20a-d. Application programs written with a 24-bit addressing schemereside in the private area 40 and use the common areas 50 and the prefixsave area 30. Since the common areas 50 do not extend above the 16 MBboundary, compatibility with previous versions of the MVS operatingsystem is preserved. Above the 16 MB boundary is a second set of commonareas 60 and an extended private area 70 which extends up to 2 GB. Thesetwo areas can only be used by programs written with a 31-bit addressingscheme in mind. They can also make use of the common area 50 and privatearea 40. For a more detailed description of the MVS operating system,reference is made to "MVS Concepts and Facilities" by Robert H. Johnson.

The 31-bit addressing scheme used in the MVS operating system is notsuitable for use in the VSE operating system if compatibility with24-bit addressing versions is to be maintained. The reasons for this liein the necessity of storage addresses in VSE to be aligned in 1 MBblocks. Thus the VSE operating system using this scheme would requireone or more 1 MB blocks starting at 0 and one or more 1 MB blocks endingat 16 MB. This would be less than the number of 1 MB blocks available asprivate areas available in current versions of the VSE operating systemand thus compatibility would not be preserved. Additionally, the "break"in the address spaces in MVS due to the common areas 50 and the extendedcommon areas 60 (MVS common areas are equivalent to VSE shared areas)complicates the use of the address spaces as it is not possible to useboth private areas as one continuous space.

SUMMARY OF THE INVENTION

The object of the invention is therefore to provide an extended memoryaddressing scheme which ensures compatibility with existing memoryaddressing schemes.

This object is achieved by splitting the shared areas required by theoperating system in the address space into two parts. One part starts atthe beginning of the address space and the other part is placed at theend of the address space. Between the two parts of the shared areas, theprivate areas of the addresses spaces are placed as one continuouslyaddressable block.

The shared areas of the address space contain a number of sharedprograms and data, including the supervisor program and the systemGETVIS space. This is an area which is reserved for system functionswhich need to acquire virtual storage dynamically during programexecution. In one embodiment of the invention, all the system functionsrequired by an applications program using 24-bit addressing are placedin the bottom part of the shared areas, whilst in another embodiment,some of the system functions are placed in the top part of the sharedareas, but are called from routines found in the bottom part of theshared areas.

The private areas of the memory may contain one or more partitions.However, in one embodiment of the invention, no partition may begin atan address greater than 16 MB to ensure that compatibility is maintainedbetween applications software running under a 31-bit addressing schemeand applications software running under a 24-bit addressing scheme.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a diagram of the 31-bit addressing scheme used in the MVSoperating system,

FIG. 2 shows a diagram of the 24-bit addressing scheme used in currentVSE operating system,

FIG. 3 shows a diagram of the 31-bit addressing scheme of the currentinvention.

FIG. 4 shows a flow diagram for calling routines in the shared areasfrom applications programs running in private areas.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 2 shows a memory structure 110 of the 24-bit addressing scheme ofthe current VSE operating System operating in ESA mode. The memorystructure 110 comprises four address spaces 120a-d. Each of the addressspaces 120a-120d has a private area 140 and access to the shared areas130 of the operating system. The private areas 140 are unique to eachaddress space 120a-d and may be divided into one or more partitions BG,F1, F2, F3, F4. The use of partitions is described in the above citedIBM Manual, Publication Number SC33-6511-00.

The shared areas 130 of the system are common to each address space120a-d and hold the supervisor 132 and, in the shared area 134, theshared virtual area and any shared partitions. The shared virtual areacontains frequently used programs and data which are available forconcurrent use by programs executing in any of the partitions BG, F1-F4.One part of the shared virtual area is reserved for the system GETVISarea. The shared partitions are partitions which contain programs thatcan be accessed from any of the private areas. One example of such aprogram is VSE/POWER which is used to spool input and output to theprivate areas.

FIG. 3 shows a memory structure 210 which is used for 31-bit addressing.The memory structure 210 below the 16 MB boundary is the same as thatshown in FIG. 2 and the same elements in the two figures are givenreference signs that differ by 100. In order to distinguish them fromtheir counterparts above the 16 MB boundary, the shared areas 230 andthe private areas 240 below the 16 MB boundary are denoted shared area(24-bit) and private area (24-bit) respectively.

FIG. 3 shows, in addition to the elements of FIG. 2, a private area(31-bit) 270 and a shared area (31-bit) 260. The private area (31-bit)270 and the shared area (31-bit) 260 have exactly the same functions astheir 24-bit counterparts. The shared area (31-bit) 270 containsfrequently used programs which are available for concurrent use byprograms executing in any of the partitions BG, F1-4. This area is,however, in general only available for use by application programs whichuse 31-bit addressing schemes. it contains no programs or data that areused by application programs written using 24-bit addressing since theseprograms cannot address this space directly. An exception to this rulewill be explained later since it may be possible for programs residingin the shared area (31-bit) 260 to be used provided there is a pointerfrom a location in the shared area (24-bit) 234.

The private area (31-bit) 270 can only be used by applications programswhich have been written for 31-bit addressing. These type of programstreat the whole of the private area, comprising both the private area(24-bit) 240 and the private area (31-bit) 270, as one continuouslyaddressable space. If an applications program is written with 24-bitaddressing, however, it can only make use of the address space up to the16 MB boundary, i.e. only the private area (24-bit) 240.

In one embodiment of the invention, no boundaries between partitions canbe placed within the private area (31-bit) 270 and thus only onepartition can occupy the private area (31-bit) 270. This ensurescompatibility with programs written for 24-bit addressing.

Due to the hardware considerations in one embodiment of the invention,the memory in a particular VSE operation system is divided into 1 MBsegments. This means that the division between the private areas 240 and270 and the shared areas 230 and 260 must occur at a 1 MB boundary. Thusin order to ensure that as much address space as possible is availableto run applications programs written for 24-bit addressing, the totalamount of address space used by the supervisor 232 and the shared area(24-bit) 234 should be rounded to just under a 1 MB boundary. Routinesand data directly required by programs written for 24-bit addressing inthe shared area must be placed. These routines can only work in 24-bitaddressing mode and thus cannot be placed in the shared area (31-bit)260. Routines using 31-bit addressing mode may also be placed in theshared area (24-bit) 234. All other routines and data are placed in theshared area (31-bit) 260. Such routines and data would include thesystem GETVIS area, phases, and system related control information suchas tables and control blocks.

Every applications program operating in VSE/ESA must be assigned twoprogram attributes: an addressing mode and a residency mode. Theaddressing mode (AMODE) is the type of addressing that is expected whenthe program (or the module within the program) is entered and can haveone of the following values:

    ______________________________________                                        AMODE 24  the program is designed to receive control in                                 24-bit addressing mode.                                             AMODE 31  the program is designed to receive control in                                 31-bit addressing mode.                                             AMODE ANY the program is designed to receive control in                                 either 24-bit or 31-bit addressing mode.                            ______________________________________                                    

The residency mode (RMODE) is a program attribute that states thevirtual storage location in which the program should reside and can haveone of the following values:

    ______________________________________                                        RMODE 24  the program is designed to reside below 16MB in                               virtual storage. VSE/ESA will place the                                       program below 16MB.                                                 RMODE ANY the program is designed to reside at any virtual                              storage location, either above or below                                       16MB. VSE/ESA places the program                                              above 16MB unless there is no suitable                                        storage above 16MB available.                                       ______________________________________                                    

Programmers can specify these attributes for new programs. Theattributes can be added to older programs if required, otherwise VSE/ESAassigns a default value when no AMODE or RMODE is specified.

At execution time there are only three valid AMODE/RMODE combinations:AMODE 24/RMODE 24, AMODE 31/RMODE 24 and AMODE 31/RMODE ANY. Of these,the combination AMODE 24/RMODE 24 is the default combination to ensurecompatibility with older programs written with 24-bit addressingschemes.

In the IBM ES/9000 series of computers, the current addressing scheme inwhich a program is operating is given by the value of the A-mode bit inthe Program Status Word (PSW). The function of the PSW and its A-modebit is described in more detail in the "IBM Enterprise SystemsArchitecture/390: Principles of Operation", IBM Corp. 1990, IBMPublication Number SA22-7201-0.

The value of the bit can be changed in a number of ways. For example,the Enterprise System Architecture of the IBM S/390 incorporates anumber of instructions which change the value of the A-mode bit duringprogram execution. These instructions allow older applications programsusing 24-bit addressing to be "glued" to newer applications programswhich use 31-bit addressing. Examples of these instructions are theBranch and Set Mode (BSM) instruction and the Branch and Save and SetMode (BASSM) instruction. Further details of their operation are givenin the above-referenced IBM publication number SA22-7201-0.

Access to the data and routines in the shared area (31-bit) 260 iscarried out in the same manner as access to the shared area (24-bit) 230and is shown in FIG. 4. From the applications program running in theprivate area (24-bit) 240 and/or the private area (31-bit), a call (step410) can be made to the supervisor 232. In the IBM S/390 EnterpriseSystem Architecture this routine is denoted "SUPERVISOR CALL" andabbreviated to SVC. For more details on the operation of this routine,reference is made to the above referenced IBM Publication NumberSA22-7201-0. It should be noted that the supervisor-call instruction isonly one example of access to data or routines in the shared areas 230and 260. Other instructions in the IBM S/390 Enterprise SystemArchitecture and in other architectures may carry out similar accesses.

The interruption caused by the supervisor-call instruction causes thecurrent PSW to be placed in an assigned storage location called theold-PSW location (step 420). A new PSW is fetched (step 430) from asecond storage location and is loaded (step 440) into the CPU (centralprocessing unit). This new PSW consists essentially of a control blockand an address. The address points (step 450) to a first-level interrupthandler which saves the system status (step 455) and in turn uses theSVC number associated with the supervisor-call interruption to look in atable stored in the supervisor 232 to find the routine indicated by theSVC number (step 460). This routine might be stored either in the sharedarea (24-bit) 234 or in the shared area (31-bit) 260 and the table willindicate the addressing mode in which the routine operates. As statedabove, the shared area in which the routine is placed depends on whetherit uses 24-bit addressing or 31-bit addressing. The routine is thencalled and run (step 470)

After completion of the routine, control is returned to the applicationsprogram from which the supervisor-call instruction was issued. This isdone by returning to the supervisor (step 480) which restores the status(step 490) and loads (step 500) the old PSW into the CPU. The nextinstruction in the applications program after the supervisor-callinstruction is then carried out (step 510).

This invention is not limited to ensuring compatibility of 24-bitaddressing scheme with 31-bit addressing schemes. It can be furtherextended to ensure compatibility of all addressing schemes using asmaller number of bits with addressing schemes using a large number ofbits. The upper shared area--in the example of the current applicationdenoted as shared area (31-bit) 260--must be accordingly moved such thatit ends at the highest addresses of the addressing scheme used andcontains routines which use such an addressing scheme. Thus the scope ofprotection of this invention is limited only by the following claims andtheir equivalents.

I claim:
 1. A method implemented in a computer system for accessingsystem functions stored in shared memory areas of an N+M bit addressedmemory region, said method comprising the steps of:defining and storinga routine and a first system function in a first shared memory areaencompassing a lowest address range of said memory region, defining andstoring a second system function in a second shared memory areaencompassing a highest address range of said memory region, and definingand storing first and second application programs in a private memoryarea spanning between said first and second shared memory areas in saidmemory region, said first application having N bit addressingencompassing said first shared memory area and said private memory areabut not said second shared memory area, and said second applicationhaving at least N+M bit addressing encompassing said first and secondshared memory areas and said private memory area; said first applicationcalling said first system function directly, said first applicationbeing precluded by said N bit addressing from calling said second systemfunction directly; and said first application calling said routine, andin response said routine calling said second system function on behalfof said first application.
 2. A method as set forth in claim 1 furthercomprising the steps of:said second application calling said firstsystem function directly; and said second application calling saidsecond system function directly.
 3. A method as set forth in claim 1wherein said first shared memory area, said private memory area and saidsecond shared memory area form a continuous address range.
 4. A methodas set forth in claim 1 further comprising the step of said routinereturning control to said first application after said second systemfunction is completed after being called by said routine on behalf ofsaid first application.
 5. A method as set forth in claim 1, whereinsaid first shared memory area also stores a supervisor program for saidfirst and second applications.
 6. A method as set forth in claim 1,wherein said first system function spools data into and out of I/Odevices.
 7. A computer system comprising:means for defining a firstshared memory area encompassing a lowest address range of a memoryregion, means for storing a routine and a first system function in saidfirst shared memory area, means for defining a second shared memory areaencompassing a highest address range of said memory region, means forstoring a second system function in said second shared memory area,means for defining a private memory area spanning between said first andsecond shared memory areas in said memory region, and means for storingfirst and second application programs in said private memory area, saidfirst application having N bit addressing encompassing said first sharedmemory area and said private memory area but not said second sharedmemory area, and said second application having at least N+M bitaddressing encompassing said first and second shared memory areas andsaid private memory area; means for calling said first system functiondirectly by said first application, said first application beingprecluded by said N bit addressing from calling said second systemfunction directly; and means for calling said routine by said firstapplication, and in response calling said second system function by saidroutine on behalf of said first application.
 8. A computer system as setforth in claim 7 further comprising:means for calling said first systemfunction directly by said second application; and means for calling saidsecond system function directly by said second application.
 9. A systemas set forth in claim 7 wherein said first shared memory area, saidprivate memory area and said second shared memory area form a continuousaddress range.
 10. A system as set forth in claim 7 further comprisingmeans for returning control from said routine to said first applicationafter said second system function is completed after being called bysaid routine on behalf of said first application.
 11. A system as setforth in claim 7, wherein said first shared memory area also stores asupervisor program for said first and second applications.
 12. A systemas set forth in claim 7, wherein said first system function spools datainto and out of I/O devices.